Design for Testability Techniques at the Behavioral and Register-Transfer Levels

Improving testability during the early stages of the design ow can have several beneets, including signiicantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high level design methodologies that consider testability during the early (behavior and architecture) stages of the design ow, and their testability beneets. The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targeting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.